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Generel CharacteristicsGenerel Characteristics: 
DesignerCompany which designed the semiconductor component MediaTek
Type Dimensity 1100 MT6891Z/CZA
Year Released 2021
FunctionMain function of the component  Multi-core Application Processor with Modem

ArchitectureArchitecture: 
Width of Machine WordMaximum bitwidth of ALU operands. Width of machine word can also be defined in different ways (register width, instruction width, etc.) in case of recent microprocessors. 64 bit
Supported Instruction Set(s) ARMv8.2-A
Type of processor core(s)Type and allocation of processor core(s) 4x ARM Cortex-A78 + 4x ARM Cortex-A55 MPcore
Number of processor core(s) octa-core

BusesBuses: 
Memory Interface(s):   LPDDR4x SDRAM
Max. Clock Frequency of Memory IFClock frequency of fastest supported memory interface 2133 MHz
Data Bus WidthMaximum selectable bit width of primary data bus (RAM) of memory interface 16 bit
Number of data bus channels 4 ch
Max. Data RateMaximal throughput of the fastest supported memory interface in 1000 megabyte per seconds units. 34.13 Gbyte/s
Non-volatile Memory InterfaceInterface which determines physical layer towards the NV memory  UFS 3.1UFS 3.1 (released as JESD220E in 2020) defines single-lane 1.45 GB/s or dual-lane 2.9 GB/s NAND flash EEPROM interface , UFS 3.1 2-laneComplies with dual-lane Universal Flash Storage 3.1 revision offering 2.9 GB/s NAND flash data rate


Clock FrequenciesClock Frequencies: 
Recommended Maximum Clock Frequency 2600 MHz max.

Cache MemoriesCache Memories: 
Total L2 CacheCapacity of level 2 cache shared between processor core(s) 1792 Kbyte L2

Technology and PackagingTechnology and Packaging: 
Feature SizeThe minimum physical dimension in the integrated circuit which can be fabricated with the given semiconductor technology 6 nm
Semiconductor Technology:   CMOSComplementary Metal-oxide - Semiconductor Field Effect Transistor
FabPlant which fabricates the semiconductor component TSMC

Graphical SubsystemGraphical Subsystem: 
Embedded GPUManufactuer (or IP designer) and type of embedded graphics coprocessor(s). ARM Mali-G77 GPU
Number of GPU cores 9-core GPU
GPU Clock 836 MHz GPU

Cellular CommunicationCellular Communication: 
Supported Cellular Data LinksList of supported cellular data links  CSDCircuit Switched Data (CSD) is the original data link protocol of GSM. Up to 9600bit/s download speed , GPRSGeneral Packet Radio Service , EDGEEnhanced Data Rates for GSM Evolution also known as Enhanced GPRS (EGPRS) , UMTSUniversal Mobile Telecommunications System. UMTS Release '99 data link layer, W-CDMA grants up to 384 kbit/s pocket-switched download speed. , HSUPAHigh-Speed Uplink Packet Access is a 3.5G UMTS uplink protocol. , HSUPA 1.4 , HSUPA 2.0 , HSUPA 5.8 , HSUPA 11.5 , HSDPAHigh-Speed Downlink Packet Access is a 3.5G UMTS downlink protocol. , HSDPA 1.8 , HSDPA 3.6 , HSDPA 7.2 , HSDPA 10.2 , HSDPA 14.4 , HSPA+ 21.1 , HSPA+ 42.2Single-carrier HSPA+ 42.2 Mbps , DC-HSDPA 42.2Dual-carrier HSPA+ 42.2 Mbps , CDMA2000 1x , CDMA2000 1xEV-DO , CDMA2000 1xEV-DO Rev A , TD-SCDMATime Division Synchronous Code Division Multiple Access is the implementation of UMTS  (3G) cellular network in China. , LTELTE (Long Term Evolution) or the E-UTRAN (Evolved Universal Terrestrial Access Network), introduced in 3GPP R8, is the 4G access part of the Evolved Packet System (EPS). , LTE 100/50LTE 100.8 Mbps / 50.4 Mbps (Cat. 3) , LTE 150/50LTE 151.2 Mbps / 50.4 Mbps (Cat. 4) , LTE 300/50More exact values: LTE 301.5 Mbps / 50.4 Mbps (Cat. 6) , LTE 300/100More exact values: LTE 301.5 Mbps / 100.8 Mbps (Cat. 7) , LTE 400/150LTE Category 13: 391.7 Mbps downlink, 150.8 Mbps uplink (rel. 12) , LTE 600/100LTE Category 12: 603 Mbps downlink, 102 Mbps uplink (Rel. 11) , LTE 1600LTE category 19, 1566 Mbps downlink, 8 CA (Rel. 13) , NR 26005G NR approx. 2.6 Gbps downlink (FR1, Sub6) , NR 37005G NR approx. 3.7 Gbps downlink , NR 46005G NR approx. 4.6 Gbps downlink data links

Additional InformationAdditional Information: 
Special Features
1x ARM Cortex-A78 (up to 2.6 GHz, 512 Kbyte L2 cache) + 3x ARM Cortex-A78 (up to 2.6 GHz, 256 Kbyte L2 cache per core) + 4x ARM Cortex-A55 (up to 2 GHz, 128 Kbyte L2 cache per core) Harvard.. ››

Datasheet AttributesDatasheet Attributes: 

Data IntegrityData integrity level determines the integrity of the published information. Final datasheets are not intended to be modified in the future, preliminary ones can be based on unofficial information or speculations, incomplete ones are also preliminary b  Preliminary
AddedThe exact time of the datasheet addition 2021-01-25 15:32
 
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