Generel Characteristics: |
|
Designer | Apple |
Type: | A10X Fusion APL1071 / APL1W71 |
Codename: | T8011 |
Year Released: | 2017 |
Function | SoC |
Architecture: |
|
Width of Machine Word | 64 bit |
Supported Instruction Set(s): | ARMv8.1-A (A32, A64) |
Type of processor core(s) | 3x Apple Hurricane + 3x Zephyr cores |
Number of processor core(s): | quad-core |
Buses: |
|
Memory Interface(s): | LPDDR4 SDRAM |
Max. Clock Frequency of Memory IF | 1600 MHz |
Data Bus Width | 64 bit |
Number of data bus channels: | 2 ch |
Max. Data Rate | 51.2 Gbyte/s |
Non-volatile Memory Interface | eMMC 5.1 , moviNAND , NAND Flash Interface , SATA |
Clock Frequencies: |
|
Recommended Maximum Clock Frequency: | 2380 MHz max. |
Cache Memories: |
|
L1 Instruction Cache per Core | 64 Kbyte I-Cache |
L1 Data Cache per Core | 64 Kbyte D-Cache |
Total L2 Cache | 3072 Kbyte L2 |
Total L3 Cache: | 8192 Kbyte L3 |
Technology and Packaging: |
|
Feature Size | 10 nm |
Semiconductor Technology: | FinFET |
Number of Transistors Integrated: | 4000000000 |
Fab | TSMC |
Graphical Subsystem: |
|
Embedded GPU | IMG PowerVR GT7600 Plus GPU |
Number of GPU cores: | 12-core GPU |
GPU Clock: | 1000 MHz GPU |
Cellular Communication: |
|
Supported Cellular Data Links | No |
Additional Information: |
|
Special Features: 3x high-performance 2.38 GHz Apple Hurricane 64-bit ARMv8-compatible (AArch32-AArch64) Harvard Superscalar processor cores (64 Kbyte L1i cache per core + 64 Kbyte L1d cache per core) + 3x high-efficiency 1.3 GHz Apple Zephyr 64-bit ARMv8-compatible (AArch32-AArch64) Harvard Superscalar processor cores.. ›› |
|
Datasheet Attributes: |
|
Data Integrity | Preliminary |
Added | 2017-06-06 18:48 |
Tweet | |