Generel Characteristics: |
Designer |
Intel |
Type: |
Core 6th Gen i3-6006U |
Codename: |
Skylake |
Year Released: |
2016 |
Function |
Multi-core Application Processor |
Architecture: |
Width of Machine Word |
64 bit |
Supported Instruction Set(s): |
IA-64 (x86-64), MMX, SSE, SSE2, SSE3, SSE4, SSE 4.1, SSE 4.2 |
Number of processor core(s): |
2 |
Type of processor core(s) |
2x Intel Skylake-U |
Buses: |
Memory Interface(s): |
DDR3L (LV) SDRAM
, mobile (LP) DDR3 SDRAM |
Data Bus Width |
64 bit |
Number of data bus channels: |
2 ch |
Non-volatile Memory Interface |
Yes |
Clock Frequencies: |
Recommended Maximum Clock Frequency: |
2000 MHz max. |
Cache Memories: |
L1 Instruction Cache per Core |
32 Kbyte I-Cache |
L1 Data Cache per Core |
32 Kbyte D-Cache |
Total L2 Cache |
512 Kbyte L2 |
Total L3 Cache: |
3072 Kbyte L3 |
Technology and Packaging: |
Feature Size |
14 nm |
Semiconductor Technology: |
CMOS |
Fab |
Intel |
Pins |
1356 pins |
Graphical Subsystem: |
Embedded GPU |
Intel Iris Graphics 520 GPU |
GPU Clock: |
300 MHz GPU |
Cellular Communication: |
Supported Cellular Data Links |
No |
Communication Interfaces: |
Supported USB Specification: |
No |
Bluetooth support |
No |
Wireless LAN support |
No |
Supported Audio/Video Interface: |
No |
Satellite Navigation: |
Supported GPS protocol(s): |
Yes |
Additional Information: |
Special Features: Dual Intel Core i5 Skylake-U processor cores, 32 Kbyte instruction cache per core, 32 Kbyte data cache per core, 256 Kbyte L2 cache per core, 3 Mbyte L3 cache (Intel Smart Cache), dual-channel 64-bit DDR4-2133, LPDDR3-1866, DDR3L-1600 SD RAM interface (max. 34.1 GB/s), Intel Hyper-Threading Technology, Intel Virtualization Technology, 300 MHz Intel Iris Graphics 520 GPU (max. 900 MHz), DirectX 12, OpenGL 4.4, Intel Clear Video HD Technology, Intel HD Audio Technology, Intel Wireless Display, Intel Insider, Intel InTru 3D Technology, Intel Quick Sync Video, Image Signal Processor, 4K eDP/DP/HDMI output support, USB 3.0 support |
Datasheet Attributes: |
Data Integrity |
Preliminary |
Added |
2016-12-06 23:10 |