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Samsung S5PC100 RISC MicroprocessorSimplified Technical Specifications
| Type: |
S5PC100 |
| Manufacturer: |
Samsung |
| Year Released: |
2009 |
| Predecessor: |
32bit Samsung S5L8900 |
Characteristics |
| CPU Structure (complexity): |
RISC |
| Width of Machine Word: |
32 bit |
| Primary (RAM) Data bus: |
32 bit |
| Secondary (ROM) Data bus: |
32 bit |
Instruction Set |
| Supported Instruction Set(s): |
ARMv7 |
| CPU Core: |
ARM Cortex-A8 |
Clock Frequencies |
| Recommanded Minimum Clock Frequency: |
600 MHz |
| Recommanded Maximum Clock Frequency: |
833 MHz |
Caches |
| Level 1 cache: |
32KiB data cache / 32 KiB instruction cache |
| Level 2 cache: |
256 KiB |
Technology |
| Semiconductor Technology: |
CMOS |
| Minimum Feature Size: |
65 nm |
Additional Details |
| Special Features: |
13-stage pipeline, 64/32-bit Multi-layer AHB/AXI bus, ARM TrustZone, NEON SIMD engine, PowerVR SGX 530 3D graphics coprocessor (100MHz), vector floating point coprocessor (VPU), 32-channel DMA |
| Related Page: |
http://www.samsung.com/global/business/semiconductor/support/brochures/downloads/systemlsi/s5pc100_brochure_200902.pdf |
| Datasheet Time: |
Jun 21, 09 11:42:21 |
| Datasheet Views: |
12197 views |
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